A 38-GHz demodulator with high image rejection in 65 nm-CMOS process

Abstract A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer proposed. In this design, the composed Wilkinson divider, series delay line with electrical length on one side and shunt 90° transmission other side. This configuration attractive because its design simplicity easy fabrication. Compared conventional techniques that utilize capacitors inductors instead line, proposed can alleviate issue variation. The demonstrates an IRR lower from 37.5 to 41.5 GHz. addition, conversion gain 1.3 ± 0.9 dB 33 41 6 dBm power. total direct current consumption 78 mW 1.0 V supply voltage. At modulation scheme 4096-QAM, 1.7% (−35.1 dB) error vector magnitude (EVM), which very close EVM measurement floor 1.6% (−36 our millimeter-wave signal analyzer.